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5
4
3
2
1
D
DRAM_D[0..15]
DRAM_A[0..11]
HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
D
SW[7..9]
U2A
HEX3_D[0..6]
U2B
C
B
DRAM_A3
DRAM_A2
DRAM_A0
DRAM_A10
DRAM_D7
DRAM_D6
DRAM_D5
DRAM_D4
DRAM_CS
DRAM_RAS
DRAM_D3
DRAM_D2
DRAM_A4
DRAM_A5
DRAM_D1
DRAM_D0
DRAM_D15
DRAM_D14
DRAM_D13
DRAM_D12
DRAM_A6
DRAM_A7
DRAM_LDQM
DRAM_WE
DRAM_A9
DRAM_CKE
DRAM_D11
DRAM_D10
DRAM_D9
DRAM_D8
DRAM_UDQM
Y4
Y3
W4
W3
Y2
Y1
W2
W1
T6
T5
V2
V1
R6
R5
U2
U1
T2
T1
R2
R1
P6
P5
R7
R8
N4
N3
P2
P1
N2
N1
M6
M5
LVDS0n
LVDS0p
LVDS1n
LVDS1p
LVDS2n
LVDS2p
LVDS3n
LVDS3p
LVDS4n
LVDS4p
LVDS5n
LVDS5p
LVDS6n
LVDS6p
LVDS7n
LVDS7p
LVDS8n
LVDS8p
LVDS9n
LVDS9p
LVDS10n
LVDS10p
LVDS11n
LVDS11p
LVDS12n
LVDS12p
LVDS13n
LVDS13p
LVDS14n
LVDS14p
LVDS15n
LVDS15p
BANK1
IO1_0
IO1_1
IO1_2
VREFB1N0
VREFB1N1
CLK3/LVDSCLK1n
CLK2/LVDSCLK1p
PLL1_OUTn
PLL1_OUTp
N6
T3
W5
P3
U3
M2
M1
V4
U4
DRAM_A11
DRAM_CAS
DRAM_A1
DRAM_A8
DRAM_BA0
SW7
SW8
DRAM_BA1
DRAM_CLK
HEX0_D0
HEX0_D1
HEX0_D2
HEX0_D3
HEX0_D4
HEX0_D5
HEX0_D6
HEX1_D0
HEX1_D1
HEX1_D2
HEX1_D3
HEX1_D4
HEX1_D5
HEX1_D6
HEX2_D0
HEX2_D1
HEX2_D2
HEX2_D3
HEX2_D5
HEX2_D4
HEX3_D6
HEX2_D6
J2
J1
H2
H1
F2
F1
E2
E1
H6
H5
H4
G3
D2
D1
G5
G6
C2
C1
E4
E3
D4
D3
LVDS16n
LVDS16p
LVDS17n
LVDS17p
LVDS18n
LVDS18p
LVDS19n
LVDS19p
LVDS20n
LVDS20p
LVDS21n
LVDS21p
LVDS22n
LVDS22p
LVDS23n
LVDS23p
LVDS24n
LVDS24p
LVDS25n
LVDS25p
LVDS26n
LVDS26p
BANK2
IO2_0
IO2_1
IO2_2
VREFB2N0
VREFB2N1
CLK1/LVDSCLK0n
CLK0/LVDSCLK0p
PLL3_OUTn
PLL3_OUTp
F3
J4
L8
F4
H3
L2
L1
D6
D5
HEX3_D5
HEX3_D3
HEX3_D4
HEX3_D0
SW9
50MHZ
HEX3_D2
HEX3_D1
C
B
A
CYCLONE II EP2C20
Title
CYCLONE II EP2C20
Altera Cyclone II Starter Board
A
Size
A
Document Number
EP2C20 BANK1 AND BANK 2
Rev
1.1A
5
4
3
Date:
Tuesday, October 03, 2006
2
Sheet
8
1
of
21
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